module ALU(
    input logic [31:0] A,
    input logic [31:0] B,
    input logic signed [31:0] signedA,
    input logic signed [31:0] signedB,
    input logic [3:0] ALUctr,
    output logic [31:0] Result,
    output logic zero
    );
    assign zero=(A-B==0);
    always_comb
        case(ALUctr)
            4'b0000:Result=A+B;
            4'b0010:Result=(signedA<signedB)?32'b1:32'b0;
            4'b0011:Result=(A<B)?32'b1:32'b0;
            4'b0110:Result=A|B;
            4'b1000:Result=A-B;
            4'b1111:Result=B;
           
        endcase
endmodule
